Complex microelectronic devices such as modern semiconductor chips require numerous connections to other electronic components. For example, a complex microprocessor chip may require many hundreds of connections to external devices. Semiconductor chips commonly have been connected to electrical traces on mounting substrates by one of three methods: wire bonding, tape automated bonding, and flip-chip bonding. In wire bonding, the chip is positioned on a substrate. Individual wires are connected between the electrical contacts on the chip and pads on the substrate. In tape automated bonding, a flexible dielectric tape with a prefabricated array of cantilever leads thereon is positioned over the chip and substrate. The individual leads are bonded to the contacts on the chip The leads are also connected to pads on the substrate. In both wire bonding and conventional tape automated bonding, the pads on the substrate are arranged outside of the area covered by the chip, so that the wires or leads fan out from the chip to the surrounding pads. The area covered by the subassembly as a whole is considerably larger than the area covered by the chip. Because the speed with which a microelectronic assembly can operate is inversely related to its size, this presents a serious drawback. Moreover, the wire bonding and tape automated bonding approaches are generally most workable with chips having contacts disposed in rows extending along the edges of the chip. They generally do not lend themselves to use with chips having contacts disposed in a so-called area array, i.e., a gridlike pattern covering all or a substantial portion of the chip front surface.
In the flip-chip mounting technique, the contact bearing top surface of the chip faces towards the substrate. Each contact on the chip is joined by a solder bond to the corresponding pad on the substrate, as by positioning solder balls on the substrate or chip, juxtaposing the chip with the substrate in the front-face-down orientation and momentarily melting or reflowing the solder. The flip-chip technique yields a compact assembly, which occupies an area of the substrate no larger than the area on the chip itself. However, flip-chip assemblies suffer from significant problems with stress caused by differential thermal expansion and contraction. The solder bonds between the chip contacts and substrate are substantially rigid. Changes in the size of the chip and of the substrate due to thermal expansion and contraction in service create substantial stresses in these rigid bonds, which in turn can lead to fatigue failure of the bonds. Moreover, it is difficult to test the chip before attaching it to the substrate, and hence difficult to maintain the required outgoing quality level in the finished assembly, particularly where the assembly includes numerous chips.
Numerous attempts have been made to solve the foregoing problems. Useful solutions are disclosed in commonly assigned U.S. Pat. Nos. 5,148,266; 5,148,265 and 5,258,330. Preferred embodiments of the structures disclosed in these patents incorporate flexible, sheetlike structures referred to as "interposers" or "chip carriers". The preferred chip carriers have a plurality of terminals disposed on a flexible, sheetlike top layer. In use, the interposer is disposed on the front or contact bearing surface of the chip with the terminals facing upwardly, away from the chip. The terminals are then connected to the contacts of the chip. Most preferably, this connection is made by bonding prefabricated leads on the interposer to the chip contacts, using a tool engaged with the lead. The completed assembly is then connected to a substrate, as by bonding the terminals of the chip carrier to the substrate. Because the leads and the dielectric layer of the chip carrier are flexible, the terminals on the chip carrier can move relative to the contacts on the chip without imposing significant stresses on the bonds between the leads and the chip, or on the bonds between the terminals and the substrate. Thus, the assembly can compensate for thermal effects. Moreover, the assembly most preferably includes a compliant layer disposed between the terminals on the chip carrier and the face of the chip itself as, for example, an elastomeric layer incorporated in the chip carrier and disposed between the dielectric layer of the chip carrier and the chip. Such a compliant structure permits displacement of the individual terminals independently towards the chip. This permits effective engagement between the subassembly and a test fixture. Thus, a test fixture incorporating numerous electrical contacts can be engaged with all of the terminals in the subassembly despite variations in the height of the terminals. The subassembly can be tested before it is bonded to a substrate so as to provide a tested, known, good part to the substrate assembly operation. This in turn provides very substantial advantages.
Despite these and other advances in the art, it would still be desirable to provide further improvements in semiconductor chip assemblies, components for such assemblies and methods of making the same. Thus, further improvement would be desirable in the ability to form bonds to the chip without damage to the chip; in the ability to connect chips with closely-spaced contacts; and in the ability to connect chips with contacts in an area array. Moreover, further improvement in the speed and reliability of the connection process would be desirable. It would also be desirable to provide similar improvements with respect to assemblies incorporating other microelectronic components. For example, certain microelectronic units such as multichip modules incorporate a rigid dielectric circuit panel having numerous contacts disposed at very small spacing. Connecting such a panel to a larger substrate poses problems similar to those encountered in mounting a semiconductor chip to the substrate and hence poses similar needs for improvement.